1. Field of the Invention
The present invention a failure detection apparatus for a solid state drive tester, and more particularly to a failure detection apparatus for a solid state drive tester which controls a plurality of memories in an interleaving manner when a storage is tested, thereby endowing a comparison operation for detecting a failure with a continuity and performing a comparison function in real time without lowering speed.
2. Description of the Related Art
Until now, hard disk drives (HDDs) have been most generally known and used as large capacity digital media storage devices. However, In recent years, as prices of NAND flash semiconductor devices, which can store the largest capacity among semiconductor devices having a memory function and data stored therein are not erased even when electric power is not supplied, are being lowered, large capacity digital media storage apparatus such as solid state drives (SSDs) using a semiconductor having a memory function are newly appearing.
Writing and reading speeds of such an SSD are 3 to 5 times as fast as those of existing hard disks, and its performance of reading/writing an random address required by a database management system is several hundreds of times as excellent as those of existing hard disks. In addition, an SSD is operated in a silent way, so a noise problem of an existing hard disk can be solved. Further, since the SSD is operated with power consumption significantly lower than that of a hard disk, the SSD is known as to most suitable for a digital device, such as a laptop computer, which requires low power consumption.
In addition, the SSD has a higher durability against an external impact than an existing hard disk, and as the SSD can be manufactured to be smaller and more various in shape as compared with a hard disk having a fixed form in terms of an external design, an external shape of an electronic product employing the SSD can be made smaller, showing many excellent advantages in its applications.
Due to its advantages, it is expected that distributions of SSDs can be expanded rapidly to searches, home shopping, storage media of video service servers, storage media for storing various R&D materials, and special equipment, as well as existing desktop computers or laptop computers.
In order to test the SSD, an SSD tester according to the related art is disclosed in FIG. 1. An SSD tester according to the related art shown in FIG. 1 includes a host terminal 110, a network 120, a test control unit 130, a memory 140. In FIG. 1, reference numeral 200 denotes a storage unit 200 including a plurality of storages 201 to 200+N which are test targets.
The host terminal 110 functions to receive a test condition for testing a storage from a user, and the network 120 is in charge of a data interface between the host terminal 110 and the test control unit 130.
The memory 140 has a program embedded therein to test the SSD, and acts as a data storage device to store pattern data used for generating test patterns and data which are generated when testing the SSD. The test control unit 130 tests a storage using a test pattern by adaptively selecting an interface according an interface type of the storage after generating the test pattern according to test conditions or randomly. In this case, preferably, a plurality of devices provided in the test control unit 130 to test the SSD are implemented in the form of one chip by using a field programmable gate array (FPGA).
More preferably, the test control unit 130 is divided into a control unit, which controls the test of the storage, and a test executing unit, which actually performs a test function, in hardware, so that a plurality of storages can be tested in real time.
The test control unit 130 includes a communication interface unit 131 connected to the host terminal 110 through the network 120 to receive user information and to transmit the test result to the host terminal 110, a storage interface unit 132 for interfacing the storage unit 200, and an embedded processor 133 for controlling storage test, and a test executing unit 160 which is connected to the embedded processor 133, generates test patterns for storage test to transmit the test patterns to a storage, and reads the test patterns out of the storage and compares the test patterns of the storage with the generated test patterns to determine the failure state of the storage test.
In addition, as illustrated in FIG. 2, the test executing unit 160 includes a pattern data generator 161, which generates pattern data by selecting one of pattern data generated under the test conditions and randomly-generated pattern data according to a pattern data select signal output from the embedded processor 133, a buffer memory 162, which temporarily stores data read out of the storage, a failure processor 163, which compares the pattern data generated from the pattern data generator 161 with the readout data temporarily stored in the buffer memory 162 to determine a failure, and generates failure information in case of a failure, a failure memory 164, which stores the failure information generated from the failure processor 163, and an instruction generator 165 which transmits a test instruction generated from the embedded processor 133 to the storage interface unit 132.
Meanwhile, the storage interface unit 132 includes a plurality of multi-interfaces 151 to 151+N. Here, internal configurations and operations of the plurality of multi-interfaces 151 to 151+N are the same, and thus only one multi-interface 151 will be described below for convenience' sake.
In the state that the test devices of the SDD having the above structure are provided in the form of one chip on one board through the FPGA, a user connects the SSD tester to a storage to be tested, inputs test condition through the host terminal 110 through the host terminal 110 in order to test the SSD. The test condition may include an interface select signal for the interface with the storage to be tested, and a test pattern select signal. The test pattern select signal is used to determine if preset pattern data are selected or if randomly-generated pattern data are selected.
The test condition of the user input through the host terminal 110 is transferred to the one-chipped test control unit 130 through the network 120.
The communication interface unit 131 of the test control unit 130 receives the test condition input by the user through the network 120, and transfers the received test condition to the embedded processor 133. If the test condition is input by the user and a test is requested, the embedded processor 133 extracts a test program for the storage test from the memory 140 and starts to test the storage. Here, as an initial operation of the test, test pattern data corresponding to the test condition input by the user are extracted from the memory 140 and transmits the test pattern to the test executing unit 160.
The test executing unit 160 is prepared by realizing a module for actually performing a test in the form of a logic separated from the embedded processor 133. As described above, the load of the embedded processor 133 can be reduced by separating the module for performing the test (generating test pattern data and determining failure) from the embedded processor 133. Accordingly, a plurality of storages can be simultaneously controlled and tested, so that the whole test time can be reduced.
In more detail, as shown in FIG. 2, the pattern data generator 161 of the test executing unit 160 generates pattern data by selecting one of pattern data generated corresponding to the test conditions and randomly-generated pattern data according to the pattern data select signal output from the embedded processor 133.
The pattern data are transmitted to the multi-interface 151 of the storage interface unit 132. The multi-interface 151 selects an interface corresponding to the storage 201 according to the interface select signal output from the embedded processor 133, transforms the pattern data in the form suitable for the selected interface, and transmits the pattern data and the test instruction to the storage 201.
Thereafter, after passing through the instruction generator 165, instruction data output from the embedded processor 133 for the test are transmitted to the storage 201 through the multi-interface 151, and though the instruction data and writing data, the storage test is started.
Next, after result data for testing the storage 201 are read out according to a reading instruction, they are transferred to the test executing unit 160 after sequentially passing through the multi-interface 151 and the embedded processor 133.
The buffer memory 162 of the test executing unit 160 temporarily stores the readout data. If the read data have been completely stored, the failure processor 163 compares expected data (pattern data) output from the pattern data generator 161 with the read data received from the embedded processor 133 according to channels by using a comparator embedded therein. If the expected data are the same as the read data, the failure processor 163 does not output the result. If the expected data differ from the read data, the failure processor 163 generates a failure signal.
An internal failure counter increases an internal failure count value by 1 based on the failure signal and outputs the failure count value, and an internal failure memory address generator generates a failure memory address to be transmitted to the failure memory 164.
The failure memory 164 stores the expectation data and the readout data input to the failure processor 163 as failure information while taking the transferred address as a logical block address (LBA).
The failure of the storage test is not processed in the embedded processor 133, but processed in the test executing unit 160 realized in the form of a logic separated from the embedded processor 133. If necessary, a plurality of pattern data can be simultaneously generated and the failure states of a plurality of storages can be simultaneously determined. Accordingly, the load of the embedded processor 133 can be reduced, and since the storages are simultaneously tested, the storage test time can be reduced.
In addition, the failure information stored in the failure memory 164 is transferred to the embedded processor 133 according to a request of the embedded processor 133, and is transmitted to the host terminal 110 through the communication interface unit 131 and the network 120.
Thus, the user can recognize the test result of the storage easily tested through the host terminal 110.
However since one buffer memory is provided according to the related art, when data input to a multi-interface are stored in the buffer memory, readout data input in real time cannot be compared with expectation data generated in a pattern generator.
For example, according to the related art, while readout data are stored in the buffer memory, a failure processor cannot determine a pass or a failure, a pass or failure can be determined by the failure processor only after all readout data are recorded in a buffer memory. Thus, since data can be read out from a storage only after an operation of reading out data from a storage is stopped while the failure processor determines a pass or failure and a pass or failure is completely determined, it is impossible to determine data of the storage in the failure processor in real time and accordingly, a time for determining a pass or failure is increased due to this.